Architecture

The moxie core implements a 32-bit load/store architecture with a compact instruction set and a simple exception model.

It provides a register file with 16 32-bit general purpose registers:

• $fp - the frame pointer
• $sp - the stack pointer
• $r1 - general purpose register
• $r2 - general purpose register
• $r3 - general purpose register
• $r4 - general purpose register
• $r5 - general purpose register
• $r6 - general purpose register
• $r7 - general purpose register
• $r8 - general purpose register
• $r9 - general purpose register
• $r10 - general purpose register
• $r11 - general purpose register
• $r12 - general purpose register
• $r13 - general purpose register

In addition, there are a number of special registers, whose values are accessible only with the Get Special Register (gsr) and Set Special Register (ssr) instructions. Some of these registers have special purposes:

• 0 - status register with the following bit values:
  • 0 - interrupts disabled flag. Set to 1 when and IRQ from the external PIC is asserted and the Exception Handler is invoked. Subsequent IRQs are ignored until this bit it cleared.
• 1 - A pointer to the Exception Handler routine (invoked by swi, IRQs, Divide by Zero and illegal instructions)
• 2 - Upon invocation of the Exception Handler (see above), special register 2 will have one of four values:
  • 0 - Divide by zero
  • 1 - Illegal instruction
  • 2 - Hardware interrupt request
  • 3 - Software interrupt
• 3 - The SWI request number (by convention only)
• 4 - Address of the supervisor mode stack on which exceptions are executed
• 5 - Return address upon entering the exception handler
• 6 -
• 7 -
• 8 -
• 9 - An optional non-zero pointer to the Device Tree blob describing this device