Index ¦ Archives ¦ Atom ¦ RSS > Category: moxie ¦ Atom

Moxie and Free Software EDA at FSOSS

I'll be speaking at FSOSS in Toronto next week on moxie and Free Software EDA tools. Check it out here: http://fsoss.senecac.on.ca/2012/node/150.


MoxieLite in Action

Brad Robinson just sent me this awesome shot of MoxieLite in action. His Xilinx Spartan-6 FPGA based SoC features a moxie core handling VGA video, keyboard and FAT-on-flash filesystem duties using custom firmware written in C. This is all in support of a second z80-based core on the same FPGA …


It's Alive!

There's a working hardware implementation of moxie in the wild!

Intrepid hacker Brad Robinson created this moxie-compatible core as a peripheral controller for his SoC. He had been using a simple 8-bit core, but needed to address more memory than was possible with the 8-bit part. Moxie is a nice …


The case against the [L]GPL for Semiconductor Core Licensing

Eli Greenbaum wrote a terrific article for the Harvard Journal of Law & Technology last fall called 'Open Source Semiconductor Core Licensing'. I'm using the GPL as a place-holder in my verilog source, but I've always felt that the GPL/LGPL were inappropriate licenses for digital logic. Eli's article makes clear …


vfork() for uClinux forces an architecture change

Moxie uses a simple software interrupt instruction (swi) to implement system calls. The swi instruction creates a call frame on the stack and then jumps to a global exception handler routine. The exception handler for moxie-uClinux switches to the kernel stack before jumping to the relevant kernel routine. Returning from …


Forking bugs

I found some time to look at the Linux kernel port again, and discovered a bug in the forking code (the child process must return 0 after a fork!). What we're looking at here is the start of userland, post kernel boot, where busybox is trying to run an init …


Multiported Registers, Microcode and Register Forwarding

When I last wrote about tackling the 'pop' instruction I noted that I needed the ability to write to multiple registers before retiring that one instruction - something that would require extra instruction cycles or loads more logic. I recently came across some work by Charles Eric LaForest on Efficient Multi-Ported …


Notes on a novel in-game CPU: the dcpu-16

The hacker behind the Minecraft phenomena, Notch, is working on his next game, most likely another hit. This one is interesting in that it includes an in-game 16-bit processor called the dcpu-16. Details are sparse, but it seems as though gamers will use this processor to control spacecraft and play …


Using the Altera USB-Blaster on Fedora

Altera's Quartus tools include some special software to download bitstreams to their devices over USB (a DE-2 eval board, in my case). They require some tricky work to set up properly on Fedora - my dev host of choice. But you're in luck! I've packaged up an RPM that takes care …


Fake RAM, load/store and push

Progress report time....

I need RAM in order to implement/test most instructions. To that end, I've implemented a fake data cache that is always accessed within a single cycle during the WRITE pipeline stage. Eventually this will have to be replaced with a real data cache that reads/writes …

© Anthony Green. Built using Pelican. Theme by Giulio Fidente on github.