When I last wrote about tackling the 'pop' instruction I noted that I needed the ability to write to multiple registers before retiring that one instruction - something that would require extra instruction cycles or loads more logic. I recently came across some work by Charles Eric LaForest on Efficient Multi-Ported …

Progress report time....

I need RAM in order to implement/test most instructions. To that end, I've implemented a fake data cache that is always accessed within a single cycle during the WRITE pipeline stage. Eventually this will have to be replaced with a real data cache that reads/writes …

A moxie-based SoC had it's first successful simulation run today....

Pretty exciting! So, here's what's happening...

The SoC, code named "Muskoka", has three main components: the moxie core, a wishbone switch and a ROM device. The switch was easy to implement, as I just have a single bus master (moxie …