Loading programs into the verilog simulation

The moxie newlib port was just accepted. The GCC port will take a little longer to review, but I hope that it will get accepted early next week. Already there has been some useful feedback resulting in a few improvements. For instance, the moxie libgcc.a now provides the soft-fp floating point emulation library instead of the fpbit one. Apparently it’s harder/better/faster/stronger, and other ports are starting to adopt it. See the “Improving Software Floating Point Support” paper from the 2006 GCC Summit Proceedings for details.

On the verilog front, I have what I believe is a first pass at the Instruction Fetch and Decode (IF/ID) units. In order to test these, you actually need real code loaded into the simulated memory. Verilog provides a handy function, $readmemh(), that sucks ASCII hex codes from a text file into a register array (fake memory). The trick is that the input file has to be in a very special format. To that end, I’ve written a new BFD write-only backend called ‘verilog’ that generates this hex dump output. So now…

  $ moxie-elf-gcc -o hello.x hello.c
  $ moxie-elf-objcopy -O verilog hello.x hello.vh

…produces a useful hello.vh, which verilog can load directly into memory like so…

module memory();
  reg [7:0] my_memory [0:64000];
  initial begin
    $readmemh("hello.vh", my_memory);
  end
endmodule;

I just submitted this to the binutils list for review. Keep your daft fingers crossed!

And this means I’m just about to start testing my IF/ID units on real code.

  • ysap

    Hi. NIce and useful addition to objcopy. I am using this for generating memory files for an M0 based system. Our system has a limitation, though that requires the file to be populated with word-sized data, instead of byte-sized data. I could not find such formatting option. Does one exist?