Time for a quick update!

"Marin" is the name of my test SoC consisting of a wishbone wrapped 75Mhz big-endian MoxieLite bus master, along with two slave devices: embedded ROM and the Nexys3's 7-segment display. So, right now I can write some code into FPGA embedded ROM to manipulate the …

Progress report time....

I need RAM in order to implement/test most instructions. To that end, I've implemented a fake data cache that is always accessed within a single cycle during the WRITE pipeline stage. Eventually this will have to be replaced with a real data cache that reads/writes …

A moxie-based SoC had it's first successful simulation run today....

Pretty exciting! So, here's what's happening...

The SoC, code named "Muskoka", has three main components: the moxie core, a wishbone switch and a ROM device. The switch was easy to implement, as I just have a single bus master (moxie …

I need to build real SoC infrastructure around my developing core in order to test it on real hardware. For the most part, this means a memory controller and IO devices. I've decided to implement a shared-bus wishbone-style interconnect for these devices. Wishbone is an open source on chip bus …