Altera's Quartus tools include some special software to download bitstreams to their devices over USB (a DE-2 eval board, in my case). They require some tricky work to set up properly on Fedora - my dev host of choice. But you're in luck! I've packaged up an RPM that takes care …
Progress report time....
I need RAM in order to implement/test most instructions. To that end, I've implemented a fake data cache that is always accessed within a single cycle during the WRITE pipeline stage. Eventually this will have to be replaced with a real data cache that reads/writes …
Tip #1 was about using an external process to perform dynamic translations of signal display values. GTKWave can also perform simple static translations of data. In the example below, for instance, moxie's execute unit is receiving a 4-bit signal identifying "register A" (riA_i) for whatever operation is about to happen …
GTKWave is a new tool for me, so I'll use this space to post useful tips as I discover them.
The first tip comes from Tony Bybell, author of GTKWave, who pointed me at some helpful functionality in a recent blog comment. You can enhance GTKWave's waveform display by replacing …
I've coded up logic for more arithmetic instructions, register moves, as well as direct and indirect jumps. For jumps, I simply pass a branch signal from the execute stage back to the fetch stage, as well as the computed target address. Here's some code that works now:
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xor $r0 …A moxie-based SoC had it's first successful simulation run today....
Pretty exciting! So, here's what's happening...
The SoC, code named "Muskoka", has three main components: the moxie core, a wishbone switch and a ROM device. The switch was easy to implement, as I just have a single bus master (moxie …
The thing about GCC is that things break when you take your eye off the ball. And this is what happened during my months long hiatus from the moxie project. Somewhere between early March and today, the moxie GCC port lost the ability to compile non-trivial code, notably libgcc. Firing …
I need to build real SoC infrastructure around my developing core in order to test it on real hardware. For the most part, this means a memory controller and IO devices. I've decided to implement a shared-bus wishbone-style interconnect for these devices. Wishbone is an open source on chip bus …
Altera's Quartus II software is now running on my Fedora box, but I was really hoping to load it into a grid of Amazon EC2 instances so I could batch out jobs for synthesis, place and route. Unfortunately the free-beer Quartus software requires a license file that is generated based …