The interrupt controller is working now, as is the timer and my exception handling firmware. So now I'm able to write a basic stop-watch application, where the 7-segment display simply increments the count every second. Yes, this sounds basic, but there's a lot of complexity under the hood! This is …

A typical software debug solution for an embedded systems might involve a JTAG connection to the board, and then some kind of protocol translation software that handles communication between GDB's remote serial protocol and the target JTAG port (see OpenOCD, for instance). The FPGA systems I'm working with include JTAG …

I've just committed the bits required to run a C program on the Marin SoC.

Rather than hook up the Nexys3 external RAM module, I'm using extra space on the FPGA itself for RAM. Most of the hard work was sorting out the linker script magic required to generate an …

Time for a quick update!

"Marin" is the name of my test SoC consisting of a wishbone wrapped 75Mhz big-endian MoxieLite bus master, along with two slave devices: embedded ROM and the Nexys3's 7-segment display. So, right now I can write some code into FPGA embedded ROM to manipulate the …

There's a working hardware implementation of moxie in the wild!

Intrepid hacker Brad Robinson created this moxie-compatible core as a peripheral controller for his SoC. He had been using a simple 8-bit core, but needed to address more memory than was possible with the 8-bit part. Moxie is a nice …

Progress report time....

I need RAM in order to implement/test most instructions. To that end, I've implemented a fake data cache that is always accessed within a single cycle during the WRITE pipeline stage. Eventually this will have to be replaced with a real data cache that reads/writes …

A moxie-based SoC had it's first successful simulation run today....

Pretty exciting! So, here's what's happening...

The SoC, code named "Muskoka", has three main components: the moxie core, a wishbone switch and a ROM device. The switch was easy to implement, as I just have a single bus master (moxie …

I need to build real SoC infrastructure around my developing core in order to test it on real hardware. For the most part, this means a memory controller and IO devices. I've decided to implement a shared-bus wishbone-style interconnect for these devices. Wishbone is an open source on chip bus …