When I last wrote about tackling the 'pop' instruction I noted that I needed the ability to write to multiple registers before retiring that one instruction - something that would require extra instruction cycles or loads more logic. I recently came across some work by Charles Eric LaForest on Efficient Multi-Ported …

I've coded up logic for more arithmetic instructions, register moves, as well as direct and indirect jumps. For jumps, I simply pass a branch signal from the execute stage back to the fetch stage, as well as the computed target address. Here's some code that works now:

.text
    xor $r0 …

A moxie-based SoC had it's first successful simulation run today....

Pretty exciting! So, here's what's happening...

The SoC, code named "Muskoka", has three main components: the moxie core, a wishbone switch and a ROM device. The switch was easy to implement, as I just have a single bus master (moxie …

I've coded up a first go at four pipeline stages so far: Fetch, Decode, Execute, and Write. After the relative complexity of the Fetch implementation, the rest has been pretty straight forward, and I've started running the first bit of compiled code through the pipline. Here's that start of our …

Moxie requires some interesting instruction fetch logic.

For my initial implementation I'm assuming a 32-bit path to instruction memory. But moxie has both 16- and 48-bit instructions, so it's not like simple RISC cores that can feed the pipeline on every cycle. My solution is to feed 32-bit instruction memory …

It's been a while since my last update. What can I say... summer was nice.

But now, back to business! I've just committed some long overdue patches to the upstream GNU tools:

• Add a device tree blob to the gdb simulator. This lets us describe the gdb sim target to …

The moxie newlib port was just accepted. The GCC port will take a little longer to review, but I hope that it will get accepted early next week. Already there has been some useful feedback resulting in a few improvements. For instance, the moxie libgcc.a now provides the soft-fp …

I've written my first bit of verilog tonight. It's not much, really, but it's a start. I'm using Icarus Verilog (iverlog) to compile and simulate the code. I also plan on using GTKWave to examine timing dumps from the iverilog simulator. Both of these tools are part of my development …

Lambda the Ultimate today posted a interesting blog entry on A Tiny Computer. It refers to 2007 paper by Chuck Thacker at Microsoft Research describing a tiny 32-bit processor. Appendix A of the paper includes the entire synthesizeable verilog implementation in just a page and a half of code! Here's …