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Moxie ports and hardware developments

It's been a while since my last update.. let me bring you up to speed.

A couple of libffi releases got in the way of moxie hacking (although libffi 3.0.13 now includes full moxie support!), but things are picking up speed again.

On the software side of things, the moxie RTEMS and QEMU ports have both been accepted upstream. So now it's possible to build, run and debug RTEMS applications on QEMU purely with upstream project sources. You may notice that I'm doing much less work in the moxiedev repository these days. This was mostly just a staging area for moxie software support (tools, OS), and there's little use for it now that most everything is upstream. All of the moxie HDL work now happens in the moxie-cores git tree.

As for the hardware side of things, here are some of the recent changes:

  • The MoxieLite core now supports ssr and gsr instructions, along with a bank of 16 special registers. The special register uses are defined here:
  • And now that the special register support is in place, exceptions and the swi (software interrupt) instruction are working in hardware. Semantics are defined here:
  • bad (illegal) instructions now cause an illegal instruction exception
  • A simple interrupt controller has been added to the marin SoC. I have the Nexys3 momentary switches hooked up as interrupt sources, so I can trigger interrupts and handle them in software by pressing those buttons.
  • A trivial timer has been hooked up to the interrupt controller, so I can now generate 'tick' interrupts for RTEMS in support of preemptive multitasking (everything was cooperative up 'til now).

I'm actually just debugging the timer ticks right now, but it's very close.

And on a final note... while RTEMS is a great little embedded RTOS, it's clear from this EE Times embedded survey that I'm going to have to implement FreeRTOS support next: I think that's what I'll tackle after I get RTEMS running preemptively.

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