You may recall that moxie supports two instructions lengths: 16- and 48-bit. Today I'm introducing a few 32-bit instructions as well.
Previously, moxie's "load and store with offset" instructions were defined as...
Load offset, long. Loads into $rA the 32-bit value from memory pointed at by …
ldo.l 00001100AAAABBBB iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
The bitcoin team has been exercising moxie in ways that it hasn't been stressed before. For example, they've been examining the code quality for their crypto libraries like libsecp256k1, an elliptical curve crypto library in C. One of their first feedbacks here was that moxie provides no native way to …
There's a working hardware implementation of moxie in the wild!
Intrepid hacker Brad Robinson created this moxie-compatible core as a peripheral controller for his SoC. He had been using a simple 8-bit core, but needed to address more memory than was possible with the 8-bit part. Moxie is a nice …
Moxie uses a simple software interrupt instruction (swi) to implement
system calls. The swi instruction creates a call frame on the stack
and then jumps to a global exception handler routine. The exception
handler for moxie-uClinux switches to the kernel stack before jumping to
the relevant kernel routine. Returning from …
The hacker behind the Minecraft phenomena, Notch, is working on his next game, most likely another hit. This one is interesting in that it includes an in-game 16-bit processor called the dcpu-16. Details are sparse, but it seems as though gamers will use this processor to control spacecraft and play …
I've coded up logic for more arithmetic instructions, register moves, as well as direct and indirect jumps. For jumps, I simply pass a branch signal from the execute stage back to the fetch stage, as well as the computed target address. Here's some code that works now:
.text
xor $r0 …A moxie-based SoC had it's first successful simulation run today....
Pretty exciting! So, here's what's happening...
The SoC, code named "Muskoka", has three main components: the moxie core, a wishbone switch and a ROM device. The switch was easy to implement, as I just have a single bus master (moxie …
I need to build real SoC infrastructure around my developing core in order to test it on real hardware. For the most part, this means a memory controller and IO devices. I've decided to implement a shared-bus wishbone-style interconnect for these devices. Wishbone is an open source on chip bus …
I've coded up a first go at four pipeline stages so far: Fetch, Decode, Execute, and Write. After the relative complexity of the Fetch implementation, the rest has been pretty straight forward, and I've started running the first bit of compiled code through the pipline. Here's that start of our …
Moxie requires some interesting instruction fetch logic.
For my initial implementation I'm assuming a 32-bit path to instruction memory. But moxie has both 16- and 48-bit instructions, so it's not like simple RISC cores that can feed the pipeline on every cycle. My solution is to feed 32-bit instruction memory …